1. Field of the Invention
The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus in which a scan integrated circuit (IC) connecting to a panel includes a first switch and a second switch, and the first switch and the second switch are simultaneously floated in a reset period, an address period, and a sustain period, thereby preventing a peaking current caused by a short-circuit of a parasitic capacitor, from being supplied to the panel.
2. Description of the Background Art
In general, a plasma display panel refers to a device for displaying an image by applying a predetermined voltage to electrodes installed in a discharge space, inducing a discharge, and exciting phosphors using plasma generated in gas discharge.
The plasma display panel has an advantage of not only facilitating scale-up and thinning but also being simplified in structure, thereby facilitating manufacture and together, providing great luminance and emission efficiency comparing to other flat display apparatus.
At present, a popular surface discharge type plasma display panel includes a scan electrode (Y), a sustain electrode (Z), and an address electrode (X). Each of the electrodes is driven by a driving unit having a scan driving circuit, a sustain driving circuit, and an address driving circuit.
In particular, the scan driving circuit includes a scan IC constituted of a first switch and a second switch. In case where a driving signal is supplied during a reset period, an address period, and a sustain period, the first switch and the second switch are complementarily switched when there are a rise and a fall to an initiation voltage of each period.
In case where the first switch and the second switch are complementarily switched, there is a drawback in that one of the first switch and the second switch is spontaneously short-circuited by a parasitic capacitor, and the first switch and the second switch are simultaneously conducted, thereby supplying a peaking current to the scan IC.